1. Technical Field of the Invention
The present invention relates to redundancy circuitry for semiconductor memory devices, and particularly to row/column redundancy circuitry for random access memory (RAM) devices.
2. Background and Objects of the Invention
Processing defects in static random access memory (SRAM) and dynamic random access memory (DRAM) devices can significantly reduce the processing yield in large scale memory arrays. In order to improve the processing yield of memory chips, various methods of error correction have been created. These include `soft` error correcting whereby software corrects for physical defects, and `hard` error correcting whereby defective circuit elements are replaced with redundant elements included on the chip. The use of soft or hard error correcting can result in lower chip manufacturing costs and earlier introduction of new products on existing wafer fabrication lines or in new process technologies.
Yield enhancement by `hard` error correcting on a memory chip is typically produced by including redundant rows and/or columns within the memory array. A few redundant rows or columns can significantly enhance yield of a memory circuit since many devices are rejected for single bit failure or failures in a single row or column. These redundant rows or columns can be added to the memory design to replace defective rows or columns which are identified at electrical test after wafer processing.
To replace a defective memory row or column, the defective row or column is first disconnected from the array. This is accomplished by one of three methods: current blown fuses, laser blown fuses, and laser annealed resistor connections. Then a redundant row or column is enabled and programmed with the defective row or column address.
Because any row or column of the memory array may be associated with a manufacturing defect, the above-described procedures for replacing a defective row or column line is conventionally carried out by providing a distinct fuse element for each row or column line. A problem exists, however, concerning the layout of the fuse elements and the memory array in that the fuse elements are large relative to the dimensions of a memory cell such that the pitch of a fuse element is generally greater than the column or row pitch for memory devices utilizing today's advanced fabrication techniques. Placing fuse elements on the column pitch has thus led to a number of compromises. One compromise, which includes replacing a number of row or column lines when only one row or column line needs to be replaced, requires the fabrication of more redundant row or column lines than would otherwise be needed. As a result, there exists a need for an improved method and circuit for replacing column or row lines in a memory device.